ADSP-SC596 datasheet(12/134 Pages) AD

12 / 134 page

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 12 of 134

May 2022

• A similar circular buffer that interrupts on fractional buf-

fers, such as at the halfway point

• The 1D DMA uses a set of identical ping pong buffers

defined by a linked ring of two-word descriptor sets, each

containing a link pointer and an address

• The 1D DMA uses a linked list of four-word descriptor sets

containing a link pointer, an address, a length, and a

configuration

• The 2D DMA uses an array of one-word descriptor sets,

specifying only the base DMA address

• The 2D DMA uses a linked list of multiword descriptor

sets, specifying all configurable parameters

Memory Direct Memory Access (MDMA)

The processor supports various memory direct memory access

(MDMA) operations, including,

• Enhanced bandwidth MDMA channels with cyclic redun-

dant code (CRC) protection (32-bit bus width, run on

SYSCLK)

• Enhanced bandwidth MDMA channel (32-bit bus width,

runs on SYSCLK)

• Maximum bandwidth MDMA channel (64-bit bus width,

runs on SYSCLK)

Extended Memory DMA

Extended memory DMA supports various operating modes,

such as delay line (which allows processor reads and writes to

external delay line buffers and to the external memory), with

limited core interaction and scatter/gather DMA (writes to and

from noncontiguous memory blocks).

Cyclic Redundancy Check (CRC) Protection

The cyclic redundancy check (CRC) protection modules allow

system software to calculate the signature of code, data, or both

in memory, the content of memory-mapped registers, or

periodic communication message objects. Dedicated hardware

circuitry compares the signature with precalculated values and

triggers appropriate fault events.

For example, the system software initiates the signature calcula-

tion of the entire memory contents every 100 ms and compares

this with expected, precalculated values. If a mismatch occurs, a

fault condition is generated through the processor core or the

trigger routing unit.

The CRC is a hardware module based on a CRC32 engine that

computes the CRC value of the 32-bit data-words presented to

it. The source channel of the memory to memory DMA (in

memory scan mode) provides data. The data can be optionally

forwarded to the destination channel (memory transfer mode).

The main features of the CRC peripheral are as follows:

• Memory scan mode

• Memory transfer mode

• Data verify mode

• Data fill mode

• User-programmable CRC32 polynomial

• Bit and byte mirroring option (endianness)

• Fault and error interrupt mechanisms

• 1D and 2D fill block to initialize an array with constants

• 32-bit CRC signature of a block of memory or an MMR

block

Event Handling

The processors provide event handling that supports both nest-

ing and prioritization. Nesting allows multiple event service

routines to be active simultaneously. Prioritization ensures that

servicing a higher priority event takes precedence over servicing

a lower priority event.

The processors provide support for four different types of

events:

• An emulation event causes the processors to enter emula-

tion mode, allowing command and control of the

processors through the JTAG interface.

• A reset event resets the processors.

• An exception event occurs synchronously to program flow

(in other words, the exception is taken before the instruc-

tion is allowed to complete). Conditions triggered by the

SHARC+ core, such as data alignment (SIMD or long

word) or compute violations (fixed or floating point) and

illegal instructions, cause core exceptions. Conditions trig-

gered by the SEC, such as error correcting code (ECC),

parity, watchdog, or system clock, cause system exceptions.

• An interrupt event occurs asynchronously to program

flow. The interrupts are caused by input signals, timers,

and other peripherals, as well as by an explicit software

instruction.

System Event Controller (SEC)

Each SHARC+ core event controller receives interrupt requests

from the system event controller (SEC). The SEC features

include the following:

• Comprehensive system event source management, includ-

ing interrupt enable, fault enable, priority, core mapping,

and source grouping

• A distributed programming model where each system

event source control and all status fields are independent of

each other

• Determinism where all system events have the same propa-

gation delay and provide unique identification of a specific

system event source

• A completer control port that provides access to all SEC

registers for configuration, status, and interrupt and fault

services

• Global locking that supports a register level protection

model to prevent writes to locked registers

• Fault management including fault action configuration,

time out, external indication, and system reset

ADSP-SC596 Datasheet(PDF) 12 Page - Analog Devices

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