ADSP-SC596 datasheet(69/134 Pages) AD

69 / 134 page

Rev. PrD

Page 69 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

PRELIMINARY TIMING SPECIFICATIONS

All specifications and characteristics apply across the entire operating conditions range unless otherwise noted.

Power-Up Reset Timing

Table 37 and Figure 7 show the relationship between power supply startup and processor reset timing, as relating to the clock generation

unit (CGU) and the reset control unit (RCU).

In Figure 7, the VDD_SUPPLIES are VDD_INT, VDD_EXT, VDD_DMC, VDD_REF, and VDD_ANA. The VDELTA_EXT_REF specification must be met at

all times, including during power-up reset and when powering down the device (Figure 8).

Table 37. Power-Up Reset Timing

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirement

tRST_IN_PWR

SYS_HWRST Deasserted after VDD_SUPPLIES (VDD_INT, VDD_EXT, VDD_DMC, VDD_REF,

VDD_ANA) and SYS_CLKIN0 are Stable and Within Specification

11 × tCKIN

Figure 7. Power-Up Reset Timing

Figure 8. Power-Up and Power-Down Voltage Delta Requirement

SYS_HWRST

tRST_IN_PWR

SYS_CLKIN0

DD_SUPPLIES

VDD_EXT

VDD_REF,

VDD_ANA

POWER-UP

POWER-DOWN

OPERATIONAL

DD_EXT

DD_REF

AND V

DD_EXT

DD_ANA

MUST NOT EXCEED V

DELTA_EXT_REF

AT ANY TIME.

ADSP-SC596 Datasheet(PDF) 69 Page - Analog Devices

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