ADSP-SC596 datasheet(15/134 Pages) AD

15 / 134 page

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 15 of 134

May 2022

DAI Routing Unit (DRU)

The DAI routing unit (DRU) provides flexibility when routing

signals across the two DAI units. All DAI0 SRU source signals

are available as source signals for the DAI1 SRU, and all DAI1

SRU source signals are available as source signals for the DAI0

SRU.

Serial Port (SPORT)

The processors feature eight synchronous serial ports

(SPORTs), providing an inexpensive interface to a wide variety

of digital and mixed-signal peripheral devices. These devices

include Analog Devices AD19xx and ADAU19xx families of

audio codecs, analog-to-digital converters (ADCs) and digital-

to-analog converters (DACs). Two data lines, a clock, and a

frame sync comprise a SPORT half. The data lines can be pro-

grammed to either transmit or receive data, and each data line

has a dedicated DMA channel.

An individual SPORT module consists of two independently

configurable SPORT halves with identical functionality. Two

bidirectional data lines—primary (0) and secondary (1)—are

available per SPORT half and are configurable as either trans-

mitters or receivers. Therefore, each SPORT half permits two

unidirectional streams into or out of the same SPORT. This

bidirectional functionality provides greater flexibility for serial

communications. For full-duplex configuration, one half

SPORT provides two transmit data signals, and the other half

SPORT provides two receive data signals. The frame sync and

clock are shared.

Serial ports operate in the following six modes:

• Standard DSP serial mode

• Multichannel time division multiplexing (TDM) mode

•I2S mode

• Packed I2S mode

• Left justified mode

• Right justified mode

Asynchronous Sample Rate Converter (ASRC)

The asynchronous sample rate converter (ASRC) contains eight

ASRC blocks. The ASRC provides up to 140 dB signal-to-noise

ratio (SNR). The ASRC block performs synchronous or asyn-

chronous sample rate conversion across independent stereo

channels, without using internal processor resources. The ASRC

blocks can also be configured to operate together to convert

multichannel audio data without phase mismatches. Finally, the

ASRC can clean up audio data from jittery clock sources such as

the S/PDIF receiver.

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The Sony/Philips Digital Interface Format (S/PDIF) is a stan-

dard audio data transfer format that allows the transfer of digital

audio signals from one device to another. There are two S/PDIF

transmit/receive blocks on the processor. The digital audio

interface carries three types of information: audio data, nonau-

dio data (compressed data), and timing information.

The S/PDIF interface supports one stereo channel or com-

pressed audio streams. The S/PDIF transmitter and receiver are

AES3 compliant and support the sample rate from 24 kHz to

192 kHz. The S/PDIF receiver supports professional jitter

standards.

The S/PDIF receiver/transmitter has no separate DMA chan-

nels. It receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the receiver/

transmitter can be formatted as left justified, I2S, or right justi-

fied with word widths of 16, 18, 20, or 24 bits. The serial data,

clock, and frame sync inputs to the S/PDIF receiver/transmitter

are routed through the SRU. They can come from various

sources, such as the SPORTs, external pins, and the precision

clock generators (PCGs), and are controlled by the SRU control

registers.

Precision Clock Generators (PCG)

The precision clock generators (PCG) consist of eight units

located in the two DAI blocks. The PCG can generate a pair of

signals (clock and frame sync) derived from a clock input signal

(CLKIN, SCLK0, or DAI pin buffer). Both units are identical in

functionality and operate independently of each other. The two

signals generated by each unit are normally used as a serial bit

clock/frame sync pair.

Pulse Density Modulation (PDM) Microphone Interface

The pulse density modulation (PDM) interface is used to con-

vert digital PDM microphone data to I2S/TDM format. The

microphone data in I2S/TDM format is then routed internally to

the serial port/ASRC or externally via the DAI pins. The PDM

microphone inputs include an internal decimation filter. Up to

eight PDM microphones can be connected to the two dedicated

digital microphone interfaces (one per DAI). Each PDM inter-

face consists of one clock line and two data lines. Two

microphones can share a single data line and be used along with

a clock line to create a dual-input microphone port. Two dual-

input lines can share a single clock line to support four micro-

phone inputs.

Enhanced Parallel Peripheral Interface (EPPI)

The processors provide an enhanced parallel peripheral inter-

face (EPPI) that supports data widths up to 24 bits. The EPPI

supports direct connection to thin film transistor (TFT) LCD

panels, parallel ADCs and DACs, video encoders and decoders,

image sensor modules, and other general-purpose peripherals.

The features supported in the EPPI module include the

following:

• Programmable data length of 8 bits, 10 bits, 12 bits, 14 bits,

16 bits, 18 bits, and 24 bits per clock

• Various framed, nonframed, and general-purpose operat-

ing modes. Frame syncs can be generated internally or can

be supplied by an external device.

• ITU-656 status word error detection and correction for

ITU-656 receive modes and ITU-656 preamble and status

word decoding

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