ADSP-SC596 datasheet(82/134 Pages) AD

82 / 134 page

Rev. PrD

Page 82 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Asynchronous Sample Rate Converter (ASRC)—Serial Input Port

The ASRC input signals are routed from the DAI0_PINx pins using the SRU. Therefore, the timing specifications provided in Table 48 are

valid at the DAI0_PINx pins.

Table 48. ASRC, Serial Input Port

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

tSRCSFS

1 The serial clock, data, and frame sync signals can originate from any of the DAI pins. The serial clock and frame sync signals can also originate via PCG or SPORTs. The

input of the PCG can be either CLKIN or any of the DAI pins.

Frame Sync Setup Before Serial Clock Rising Edge

tSRCHFS

Frame Sync Hold After Serial Clock Rising Edge

5.5

tSRCSD

Data Setup Before Serial Clock Rising Edge

tSRCHD

Data Hold After Serial Clock Rising Edge

5.5

tSRCCLKW

Clock Width

tSCLK0 – 1

tSRCCLK

Clock Period

2 × tSCLK0

Figure 18. ASRC Serial Input Port Timing

DAI0_PIN20–1

(SCLK0)

SAMPLE EDGE

DAI0_PIN20–1

(FS)

DAI0_PIN20–1

(SDATA)

tSRCCLK

tSRCCLKW

tSRCSFS

tSRCHFS

tSRCHD

tSRCSD

ADSP-SC596 Datasheet(PDF) 82 Page - Analog Devices

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