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ADSP-SC596 Datasheet(PDF) 88 Page - Analog Devices |
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ADSP-SC596 Datasheet(HTML) 88 Page - Analog Devices |
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88 / 134 page  Rev. PrD | Page 88 of 134 | May 2022 ADSP-SC595/SC596/SC598 Preliminary Technical Data SPI Port—SPIx_RDY Slave Timing SPIx_RDY provides flow control. CPOL, CPHA, and FCCH are configuration bits in the SPIx_CTL register. Table 52. SPI Port—SPIx_RDY Slave Timing1 1 All specifications apply to all three SPIs. All specifications are based on simulation data and are subject to change without notice. Parameter Conditions Min Max Unit Switching Characteristic tDSPISCKRDYS SPIx_RDY Deassertion From Last Valid Input SPIx_CLK Edge FCCH = 0 3 × tCDU_CLKO6 4 × tCDU_CLKO6 + 10 ns FCCH = 1 4 × tCDU_CLKO6 5 × tCDU_CLKO6 + 10 ns Figure 22. SPIx_RDY Deassertion from Valid Input SPIx_CLK Edge in Slave Mode SPIx_CLK (CPOL = 0) SPIx_CLK (CPOL = 1) tDSPISCKRDYS SPIx_RDY (O) SPIx_CLK (CPOL = 0) SPIx_CLK (CPOL = 1) CPHA = 1 CPHA = 0 |
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