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ADSP-SC596 Datasheet(PDF) 32 Page - Analog Devices |
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ADSP-SC596 Datasheet(HTML) 32 Page - Analog Devices |
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32 / 134 page  ADSP-SC595/SC596/SC598 Preliminary Technical Data Rev. PrD | Page 32 of 134 | May 2022 EMSI0_CLK EMSI0 Clock E PE_09 EMSI0_CMD EMSI0 Command G PG_01 EMSI0_D0 EMSI0 Data 0 D PD_15 EMSI0_D1 EMSI0 Data 1 E PE_01 EMSI0_D2 EMSI0 Data 2 E PE_06 EMSI0_D3 EMSI0 Data 3 E PE_08 EMSI0_D4 EMSI0 Data 4 G PG_02 EMSI0_D5 EMSI0 Data 5 G PG_08 EMSI0_D6 EMSI0 Data 6 G PG_09 EMSI0_D7 EMSI0 Data 7 G PG_10 EMSI0_RST EMSI0 Reset C PC_04 EMSI0_WP EMSI0 Write Protect C PC_06 ETH0_COL EMAC0 MII Collision Detect D PD_07 ETH0_CRS EMAC0 MII Carrier Sense D PD_02 ETH0_MDC EMAC0 Serial Management Clock H PH_03 ETH0_MDIO EMAC0 Serial Management Bidirectional Data H PH_04 ETH0_PHY_INT EMAC0 PHY Interrupt D PD_12 ETH0_PTPAUX_MCG_IN0 EMAC0 PTP Auxiliary/Media Clock Generation Trigger Input 0 I PI_02 ETH0_PTPAUX_MCG_IN1 EMAC0 PTP Auxiliary/Media Clock Generation Trigger Input 1 D PD_05 ETH0_PTPAUX_MCG_IN2 EMAC0 PTP Auxiliary/Media Clock Generation Trigger Input 2 D PD_03 ETH0_PTPAUX_MCG_IN3 EMAC0 PTP Auxiliary/Media Clock Generation Trigger Input 3 E PE_09 ETH0_PTPCLKIN0 EMAC0 PTP Clock Input 0 I PI_01 ETH0_PTPPPS0 EMAC0 Pulse Per Second Output 0 I PI_04 ETH0_PTPPPS1 EMAC0 Pulse Per Second Output 1 I PI_03 ETH0_PTPPPS2 EMAC0 Pulse Per Second Output 2 I PI_05 ETH0_PTPPPS3 EMAC0 Pulse Per Second Output 3 I PI_06 ETH0_RXCLK_REFCLK EMAC0 RXCLK (10/100/1000) or REFCLK (10/100) H PH_07 ETH0_RXCTL_CRSRX_DV EMAC0 RXCTL (RGMII) or CRS_DV (GMII) or RX_DV (MII) H PH_08 ETH0_RXD0 EMAC0 Receive Data 0 H PH_05 ETH0_RXD1 EMAC0 Receive Data 1 H PH_06 ETH0_RXD2 EMAC0 Receive Data 2 H PH_11 ETH0_RXD3 EMAC0 Receive Data 3 H PH_12 ETH0_RXERR EMAC0 Receive Error D PD_06 ETH0_TXCLK EMAC0 Transmit Clock H PH_14 ETH0_TXCTL_TXEN EMAC0 TXCTL (10/100/1000) or TXEN (10/100) H PH_13 ETH0_TXD0 EMAC0 Transmit Data 0 H PH_09 ETH0_TXD1 EMAC0 Transmit Data 1 H PH_10 ETH0_TXD2 EMAC0 Transmit Data 2 H PH_15 ETH0_TXD3 EMAC0 Transmit Data 3 I PI_00 ETH1_CRS EMAC1 Carrier Sense F PF_03 ETH1_MDC EMAC1 Serial Management Clock F PF_02 ETH1_MDIO EMAC1 Serial Management Bidirectional Data F PF_01 ETH1_REFCLK EMAC1 Reference Clock E PE_11 ETH1_RXD0 EMAC1 Receive Data 0 E PE_15 ETH1_RXD1 EMAC1 Receive Data 1 F PF_00 ETH1_TXD0 EMAC1 Transmit Data 0 E PE_13 ETH1_TXD1 EMAC1 Transmit Data 1 E PE_14 ETH1_TXEN EMAC1 Transmit Enable E PE_12 Table 10. ADSP-SC595/SC596/SC598 400-Ball BGA_ED Signal Descriptions (Continued) Signal Name Description Port Pin Name |
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