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ADSP-SC596 Datasheet(PDF) 39 Page - Analog Devices |
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ADSP-SC596 Datasheet(HTML) 39 Page - Analog Devices |
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39 / 134 page  ADSP-SC595/SC596/SC598 Preliminary Technical Data Rev. PrD | Page 39 of 134 | May 2022 GPIO MULTIPLEXING FOR 400-BALL BGA_ED PACKAGE Table 11 through Table 19 identify the pin functions that are multiplexed on the GPIO pins of the 400-ball BGA_ED package. Table 11. ADSP-SC595/SC596/SC598 Signal Multiplexing for Port A Signal Name Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Multiplexed Function 3 Multiplexed Function Input Tap PA_00 SPI2_MISO OSPI0_MISO1 PA_01 SPI2_MOSI OSPI0_MOSI1 PA_02 SPI2_D2 OSPI0_D21 TWI3_SCL1 TM0_ACLK03 PA_03 SPI2_D3 OSPI0_D31 TWI3_SDA1 PA_04 SPI2_CLK OSPI0_CLK1 PA_05 SPI2_SEL1 OSPI0_SEL12 SPI2_SS PA_06 SPI0_CLK UART0_TX1 OSPI0_D41 TM0_ACLK01 PA_07 SPI0_MISO UART0_RX1 OSPI0_D51 TM0_ACI00 PA_08 SPI0_MOSI UART0_RTS1 OSPI0_D61 TM0_ACLK02 PA_09 SPI0_SEL1 UART0_CTS1 OSPI0_D71 SPI0_SS PA_10 TWI0_SCL1 SPI1_CLK TM0_TMR00 PA_11 TWI0_SDA1 SPI1_MISO HADC0_EOC_DOUT TM0_ACI04 PA_12 C1_FLG00 SPI1_MOSI TM0_TMR01 PA_13 C1_FLG01 SPI1_SEL1 TM0_TMR02 SPI1_SS PA_14 TWI2_SCL1 SPI1_D2 UART1_RX1 TM0_ACI01 PA_15 TWI2_SDA1 SPI1_D3 UART1_TX1 1 To ensure proper timing, for peripherals whose signals are available at multiple places in the pin mux, care must be taken to select all needed signals of the peripheral so that their associated pins are as close as possible to each other. 2 These peripheral signals are available at multiple places in the pin mux. These signals can be selected from either of the two locations in pin mux, regardless of proximity to other associated signals of the same peripheral. Table 12. ADSP-SC595/SC596/SC598 Signal Multiplexing for Port B Signal Name Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Multiplexed Function 3 Multiplexed Function Input Tap PB_00 MLB0_DAT TWI1_SCL1 UART1_RTS1 TM0_ACI03 PB_01 MLB0_SIG TWI1_SDA1 UART1_CTS1 TM0_CLK PB_02 MLB0_CLK C1_FLG03 LP1_ACK TM0_ACLK04 PB_03 TM0_TMR03 C1_FLG02 SPI2_SEL22 CNT0_UD PB_04 TM0_TMR04 SPI1_RDY2 LP0_ACK CNT0_ZM PB_05 TM0_TMR05 SPI2_RDY2 SPI0_SEL2 CNT0_DG PB_06 LP0_CLK SPI1_SEL5 TRACE0_CLK PB_07 LP0_D0 SPI2_SEL5 TRACE0_D00 PB_08 LP0_D1 SPI1_SEL72 TM0_TMR06 TRACE0_D01 PB_09 LP0_D2 SPI2_SEL72 TM0_TMR07 TRACE0_D02 PB_10 LP0_D3 SPI1_SEL2 TRACE0_D03 PB_11 LP0_D4 SPI0_RDY2 UART2_RX1 TM0_ACI02 PB_12 LP0_D5 SPI2_SEL32 UART2_TX1 PB_13 LP0_D6 SPI1_SEL3 OSPI0_DQS1 UART2_RTS1 PB_14 LP0_D7 SPI0_SEL3 UART2_CTS1 PB_15 LP1_D0 SPI0_SEL4 EMSI0_CD 1 To ensure proper timing, for peripherals whose signals are available at multiple places in the pin mux, care must be taken to select all needed signals of the peripheral so that their associated pins are as close as possible to each other 2 These peripheral signals are available at multiple places in the pin mux. These signals can be selected from either of the two locations in pin mux, regardless of proximity to other associated signals of the same peripheral. |
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