ADSP-SC596 datasheet(7/134 Pages) AD

7 / 134 page

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 7 of 134

May 2022

these caches are independently configurable from 0 to 128 kB

each. The memory not managed by the cache controllers is

directly addressable by the processors. The controllers ensure

the data coherence between the two data caches. The caches

provide user controllable features such as full and partial lock-

ing, range bound invalidation, and flushing.

Core Memory-Mapped Registers (CMMR)

The core memory-mapped registers (CMMR) control the

L1 instruction and data cache, branch target buffer (BTB),

L2 cache, parity error, system control, debug, and monitor

functions.

SHARC+ CORE ARCHITECTURE

The ADSP-SC595/SC596/SC598 processors are assembly code

compatible with all previous SHARC processors featuring the

SHARC or SHARC+ core, beginning with the first generation

ADSP-2106x SHARC processors and including the ADSP-

2116x, ADSP-2126x, ADSP-213xx, ADSP-214xx, and ADSP-

SC5xx/ADSP-215xx processors.

The SIMD architecture featured on the ADSP-

SC595/SC596/SC598 processors is identical to all previous

SIMD SHARC processors, namely the ADSP-2116x, ADSP-

2126x, ADSP-213xx, ADSP-214xx, and ADSP-SC5xx/ADSP-

215xx processors, as shown in Figure 3 and as described in the

following sections.

Single-Instruction, Multiple Data (SIMD) Computational

Engine

The SHARC+ core contains two computational processing ele-

ments that operate as a single-instruction, multiple data (SIMD)

engine.

The processing elements are referred to as PEx and PEy, each

containing an arithmetic logic unit (ALU), multiplier, shifter,

and register file. PEx is always active, and PEy is enabled by set-

ting the PEYEN mode bit in the mode control register

(MODE1).

SIMD mode allows the processors to execute the same instruc-

tion in both processing elements, but each processing element

operates on different data. This architecture efficiently executes

math intensive DSP algorithms. In addition to all the features of

previous generation SHARC cores, the SHARC+ core also pro-

vides a new and simpler way to execute an instruction only on

the PEy data register.

SIMD mode doubles the bandwidth between memory and the

processing elements, as required for sustained computational

operation of two processing elements. When using the data

address generators (DAGs) to transfer data in SIMD mode, two

data values transfer with each memory or register file access.

Independent Parallel Computation Units

Within each processing element is a set of pipelined computa-

tional units. The computational units consist of a multiplier, an

ALU, and a shifter. These units are arranged in parallel, maxi-

mizing computational throughput. These computational units

support IEEE 32-bit single-precision floating-point; 40-bit

extended-precision floating-point; IEEE 64-bit double-preci-

sion floating-point; and 32-bit fixed-point data formats.

A multifunction instruction set supports parallel execution of

the ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments per core.

All processing operations take one cycle to complete. For all

floating-point operations, the processor takes two cycles to

complete in case of data dependency. Double-precision float-

ing-point data take two to six cycles to complete. The processor

stalls for the appropriate number of cycles for an interlocked

pipeline plus data dependency check.

Figure 4. ADSP-SC595/SC596/SC598 Memory Map

RESERVED

0x FFFF FFFF

0x C000 0000

0x 8000 0000

0x 6000 0000

0x 5000 0000

0x 4C00 0000

0x 4800 0000

0x 4400 0000

0x 4000 0000

0x 3000 0000

0x 2840 0000

0x 2824 0000

0x 2023 0000

0x 2020 0000

DMC0 (1GB)

SPI2/OSPI0 FLASH ADDRESS SPACE (512MB)

SYSTEM MMR

SHARC2 L1 ADDRESS SPACE VIA

COMPLETER PORT 1/COMPLETER PORT 2

SHARC1 L1 ADDRESS SPACE VIA

COMPLETER PORT 1/COMPLETER PORT 2

RESERVED

L2 SRAM (16Mb)

RESERVED

L2 BOOT ROM 1 (0.5Mb)

L2 BOOT ROM 0 (0.5Mb)

L2 BOOT ROM 2 (0.5Mb)

0x 2022 0000

0x 2021 0000

0x 2000 0000

0x 0039 FFFF

0x 0038 0000

0x 0031 FFFF

0x 0030 0000

0x 002E FFFF

0x 002C 0000

0x 0026 FFFF

0x 0024 0000

0x 0000 0000

RESERVED

L1 BLOCK 3 SRAM (1Mb)

RESERVED

L1 BLOCK 2 SRAM (1Mb)

L1 BLOCK 1 SRAM (1.5Mb)

L1 BLOCK 0 SRAM (1.5Mb)

RESERVED/CORE MMRs/

OTHER MEMORY ALIASES

RESERVED

ARM L2 CONFIG REGS (4KB)

RESERVED

ARM BOOT (64KB)

0x 2000 0000

0x 1000 1000

0x 1000 0000

0x 0000 FFFF

0x 0000 0000

0x 28BA 0000

0x 28A4 0000

**FOR THE ADSP-SC595,THE 1MB (8Mb) L2 SRAM RANGE IS 0x20100000–0x201FFFFF.

(ARM BOOT ALIAS ADDRESS SPACE)

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