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ADSP-SC596 Datasheet(PDF) 4 Page - Analog Devices

Part # ADSP-SC596
Description  SHARC Dual-Core DSP with Arm Cortex-A55
PDF  134 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-SC596 Datasheet(HTML) 4 Page - Analog Devices

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ADSP-SC595/SC596/SC598
Preliminary Technical Data
Rev. PrD
|
Page 4 of 134
|
May 2022
Table 1. Processor Features1
Processor Feature
ADSP-SC595
ADSP-SC596
ADSP-SC598
Arm Cortex-A55 (MHz, Maximum)2
1200
Arm Core L1 Cache (I, D kB)
32, 32
Arm Core L2 Cache (kB)
256
SHARC+ Core1 (MHz, Maximum)2
600, 812.5
1000
812.5, 1000
SHARC+ Core2 (MHz, Maximum)2
N/A
SHARC L1 SRAM (kB)
1 × 640
2 × 640
System Memory
L2 SRAM (Shared) (MB)
1
2
DDR3/DDR3L Controller (16-Bit)
1
Hardware Accelerators
FIR
1 per SHARC+ core
IIR
4 per SHARC+ core
Security Cryptographic Engine
Yes
DAI (Includes SRU and DRU)
2
Full SPORTs
8 (4 per DAI)
S/PDIF Receive/Transmit
2 (1 per DAI)
ASRCs
8 (4 per DAI)
4-Channel PDM Microphone (MIC) Input
2 (1 per DAI)
PCGs
8 (4 per DAI)
Pin Buffers
40 (20 per DAI)
Multiplexed Peripherals
MLB 3-Pin
Yes3
eMSI (eMMC)
1
Link Ports
2
GP Counter
1
I2C (TWI)
6
Watchdog Timers
3
GP Timers
16
Octal SPI
1
Quad-Data Bit SPI
2
Dual-Data Bit SPI
2
UARTs
4
ePPI
1
USB 2.0 HS OTG Controller
1
EMAC Std
10/100
EMAC Std/AVB + Timer IEEE 1588
10/100/1000
CAN FD
23
MLB 6-Pin
Yes3
Multichannel 12-Bit ADC
8-channel4
GPIO Ports
Port A to Port I
GPIO + DAI Pins
135 + 40
Package Options
400- ball BGA_ED
1 N/A means not applicable.
2 Multiple values indicate various speed grades. See Planned Automotive Production Products, Planned Production Products, and Pre Release Products.
3 Applies to automotive models only. See Planned Automotive Production Products.
4 The HADC can support up to 7 additional channels using an external multiplexer.



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